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advance product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. copyright ? cirrus logic, inc. 2007 (all rights reserved) http://www.cirrus.com 7/31/07 CS5560 2.5 v / 5 v, 50 ksps, 24-bit, high-throughput ? adc features & description ? differential analog input ? on-chip buffers for high input impedance ? conversion time = 20 s ? settles in one conversion ? linearity error = 0.0007% ? signal-to-noise = 110 db ? 24 bits, no missing codes ? self-calibration: - maintains accuracy over time & temperature. ? simple three/four-wire serial interface ? power supply configurations: - analog: +5v/gnd; io: +1.8v to +3.3v - analog: 2.5v; io : +1.8v to +3.3v ? power consumption: - adc input buffers on: 85 mw - adc input buffers off: 70 mw general description the CS5560 is a single-channel, 24-bit analog-to-digital converter capable of 50 ksps conversion rate. the input accepts a fully differential analog input signal. on-chip buffers provide high input im pedance for both the ain in- puts and the vref+ input. this significantly reduces the drive requirements of signal sources and reduces errors due to source impedances. the CS5560 is a delta-sigma converter capable of switchi ng multiple input channels at a high rate with no loss in throughput. the adc uses a low-latency digital filter architecture. the filter is designed for fast settling and settles to full accuracy in one conver- sion. the converter's 24-bit data output is in serial form, with the serial port acting as either a master or a slave. the converter is designed to support bipolar, ground-refer- enced signals when operated from 2.5v analog supplies. the CS5560 uses self-calibration to achieve low offset and gain errors. the converter achieves a s/n of 110 db. lin- earity is 0.0007% of full scale. the converter can operate from an analog supply of 0-5v or from 2.5v. the digital interface supports standard log- ic operating from 1.8, 2.5, or 3.3 v. ordering in formation: see ordering information on page 32. ain+ ain- cs sdi sclk smode vref+ vref- rdy osc/clock generator conv cal bp/up calibration microcontroller serial interface adc digital filter logic vl mclk sdo rst sleep dcr vlr v1- v2- bufen v2+ v1+ CS5560 aug ?07 ds713a5
CS5560 2 ds713a5 7/31/07 table of contents 1. characteristics and spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 analog characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 digital characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 guaranteed logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 reset and calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.1.1 offset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.2 gain register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.5 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 output coding format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 3.7 typical connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 ain & vref sampling structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 converter performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 3.10 digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11 serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11.1 ssc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11.2 sec mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.12 power supplies & grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 using the CS5560 in multiplexing applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14 synchronizing multiple converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7. environmental, manufact uring, & handling information . . . . . . . . . . . . . . 32 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CS5560 ds713a5 3 7/31/07 list of figures figure 1. ssc mode - read timing, cs remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. ssc mode - read timing, cs falling after rdy falls . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. sec mode - read timing (not to scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. sec mode - calibration regist er read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. sec mode - write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. voltage reference circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 7. CS5560 configured using 2.5v analog supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. CS5560 configured using a single 5v analog su pply . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. CS5560 dnl plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. CS5560 spectral response (dc to fs/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. CS5560 spectral response (dc to 5 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. CS5560 spectral response (dc to 4fs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. simple multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 14. more complex multip lexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 list of tables table 1. offset & gain calibration register read/write commands . . . . . . . . . . . . . . . . . . . . . . 16 table 2. output coding, two?s complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3. output coding, offset binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CS5560 4 ds713a5 7/31/07 1. characteristics and specifications ? min / max characteristics and spec ifications are guaranteed over th e specified operating conditions. ? typical characteristics and specifications are measured at nominal supply voltages and t a = 25c. ? vlr = 0 v. all voltages with respect to 0 v. analog characteristics t a = -40 to +85 c; v1+ = v2+ = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl -vlr = 3.3 v, 5%; vref = (vref+) - (vref-) = 4.096v; mclk = 16 mhz; smode = vl. bufen = v1+ unless otherwise stated. connected per figure 7 . bipolar mode unless otherwise stated. 1. applies after calibration at any temperature within -40 c to +85 c. 2. no missing codes is guaranteed at 24 bits re solution over the specified temperature range. 3. total drift over specified temperature ran ge after calibration at power-up, at 25o c. 4. scales with mclk. parameter min typ max unit accuracy linearity error (note 1) - 0.0003 - %fs differential linearity error (note 2) - 0.1 - lsb 24 positive full-scale error after reset after calibration (note 1) - - 1.0 0.01 - %fs negative full-scale error after reset after calibration (note 1) - - 1.0 0.01 - %fs full-scale drift (note 3) - - lsb 24 unipolar offset after reset after calibration (note 1) - - 2000 400 - - lsb 24 unipolar offset drift (note 3) - - lsb 24 bipolar offset after reset after calibration (note 1) - - 1000 200 - - lsb 24 bipolar offset drift (note 3) - - lsb 24 noise - 9.5 - vrms dynamic performance peak harmonic or spurious noise 1 khz, -0.5 db input - -110 - db total harmonic distortion 1 khz, -0.5 db input - -110 - db signal-to-noise - 110 - db s/(n + d) ratio -0.5 db input, 1 khz -60 db input, 1 khz - - 107 48 - - db db -3 db input bandwidth (note 4) - 42 - khz
CS5560 ds713a5 5 7/31/07 analog characteristics (continued) t a = -40 to +85 c; v1+ = v2 + = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl -vlr = 3.3 v, 5%; vref = ( vref+) - (vref-) = 4.096v; mclk = 16 mhz; smode = vl.; bufen = v1+ unless otherwise stated. connected per figure 7 . 5. measured using an input signal of 1 v dc. 6. for optimum performance, vref+ should always be less than (v+) - 0.2 volts to prevent saturation of the vref+ input buffer. 7. tested with 100 mvp-p on any supply up to 1 khz. v1+ and v2+ supplies at the same voltage potential, v1- and v2- supplies at the same voltage potential. parameter min typ max unit analog input analog input range unipolar bipolar 0 to +vref vref v v input capacitance - 10 - pf cvf current (note 5) ain buffer on (bufen = v+) ain buffer off (bufen = v-) acom - - - 600 130 130 - - - na a a voltage reference input voltage reference input range (vref+) ? (vref-) (note 6) 2.4 4.096 4.2 v input capacitance - 10 - pf cvf current vref+ buffer on (bufen = v+) vref+ buffer off (bufen = v-) vref- - - - 3 1 1 - - - a ma ma power supplies dc power supply currents i v1 i v2 i vl - - - - - - 18 1.8 0.5 ma ma ma power consumption normal operation buffers on buffers off - - 85 70 105 90 mw mw power supply rejection (no te 7) v1+ , v2+ supplies v1-, v2- supplies 90 90 110 110 - - db db
CS5560 6 ds713a5 7/31/07 switching characteristics t a = -40 to +85 c; v1+ = v2+ = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v; logic 1 = vd+; cl = 15 pf. 8. cal can be controlled by the same signal used for rst . if cal goes high simultaneously with rst , a calibration will be performed, but cal must remain high until rdy falls. 9. bp/up can be changed coincident conv falling. bp/up must remain stable until rdy falls. 10. if conv is held low continuously, conversions occur every 320 mclk cycles. if rdy is tied to conv , conversions will occur every 322 mclks. if conv is operated asynchronously to mclk, a conversion may take up to 324 mclks. rdy falls at the end of conversion. 11. rdy will fall when the device is fully operational when coming out of sleep mode. parameter symbol min typ max unit master clock frequenc y internal oscillator external clock xin f clk 12 0.5 14 16 16 16.2 mhz mhz master clock duty cycle 40 - 60 % reset rst low time t res 1- -s rst rising to rdy falling internal oscillator external clock t wup - - 120 1536 - - s mclks calibration cal pulse width (note 8) t pw 4- -mclks cal high setup time to rst rising (note 8) t ccw 0- -ns calibration time rst rising (cal high) to rdy falling t scl - 331458 - mclks calibration time cal rising (rst high) to rdy falling t cal - 331458 - mclks conversion conv pulse width t cpw 4- -mclks bp/up setup to conv falling (note 9) t scn 0- -ns conv low to start of conversion t scn --2mclks perform single conversion (conv high before rdy falling) t bus 20 - - mclks conversion time (note 10) start of conversion to rdy falling t buh --324mclks sleep mode sleep low to low-power state sleep high to device active (note 11) t con t con - - 50 3083 - - s mclks
CS5560 ds713a5 7 7/31/07 switching characteristics (continued) t a = -40 to +85 c; v1+ = v2+ = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v; logic 1 = vd+; cl = 15 pf. 12. sdo and sclk will be high impedance when cs is high. in some systems it ma y require a pull-down resister. 13. sclk = mclk/2. parameter symbol min typ max unit serial port timing in ssc mode (smode = vl) rdy falling to msb stable t 1 --2-mclks data hold time after sclk rising t 2 -10-ns serial clock (out) pulse width (low) (note 12, 13) pulse width (high) t 3 t 4 50 50 - - - - ns ns rdy rising after last sclk rising t 5 -8-mclks mclk rdy sclk(o) sdo msb msb ? 1 lsb lsb+1 cs t 1 t 2 t 3 t 4 t 5 figure 1. ssc mode - read timing, cs remaining low (not to scale)
CS5560 8 ds713a5 7/31/07 switching characteristics (continued) t a = -40 to +85 c; v1+ = v2+ = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v; logic 1 = vd+; cl = 15 pf. 14. sdo and sclk will be high impedance when cs is high. in some systems it ma y require a pull-down resister. 15. sclk = mclk/2. parameter symbol min typ max unit serial port timing in ssc mode (smode = vl) data hold time after sclk rising t 7 -10-ns serial clock (out) pulse width (low) (note 14, 15) pulse width (high) t 8 t 9 50 50 - - - - ns ns rdy rising after last sclk rising t 10 -8-mclks cs falling to msb stable t 11 -10-ns first sclk rising after cs falling t 12 -8-mclks cs hold time (low) after sclk rising t 13 10 - - ns sclk, sdo tristate after cs rising t 14 -5-ns mclk rdy sclk(o) sdo cs t 12 t 8 t 13 t 9 t 7 t 11 msb msb ? 1 lsb lsb+1 t 14 t 10 figure 2. ssc mode - read timing, cs falling after rdy falls (not to scale)
CS5560 ds713a5 9 7/31/07 switching characteristics (continued) t a = -40 to +85 c; v1+ = v2+ = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v; logic 1 = vd+; cl = 15 pf. 16. sdo will be high impedance when cs is high. in some systems it may require a pul l-down resistor. parameter symbol min typ max unit serial port timing in sec mode (smode = vlr) sclk(in) pulse width (high) - 30 - - ns sclk(in) pulse width (low) - 30 - - ns cs hold time (high) after rdy falling t 15 10 - - ns cs hold time (high) after sclk rising t 16 10 - - ns cs low to sdo out of hi-z (note 16) t 17 -10-ns data hold time after sclk rising t 18 -10-ns data setup time before sclk rising t 19 10 - - ns cs hold time (low) after sclk rising t 20 10 - - ns rdy rising after sclk falling t 21 -10-ns mclk sclk(i) sdo cs rdy lsb msb t 19 t 18 t 20 t 17 t 16 t 15 t 21 figure 3. sec mode - read timing (not to scale)
CS5560 10 ds713a5 7/31/07 switching characteristics (continued) t a = -40 to +85 c; v1+ = v2+ = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v; logic 1 = vd+; cl = 15 pf. parameter symbol min typ max unit calibration register read timing cs hold time (high) after sclk rising t 22 10 - ns data setup time before sclk rising t 23 10 - - ns data hold time after sclk rising t 24 10 - - ns sclk rising to data stable t 25 -10-ns data hold time after sclk rising t 26 -10-ns sclk rising to cs rising t 27 10 - - ns sdo tristate after cs rising t 28 -5-ns sclk(i) sdi cs lsb msb msb command time 8 sclks data time 24 sclks sdo t 22 t 24 t 23 t 27 t 25 t 26 t 28 lsb figure 4. sec mode - calibration register read timing (not to scale)
CS5560 ds713a5 11 7/31/07 switching characteristics (continued) t a = -40 to +85 c; v1+ = v2+ = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v; logic 1 = vd+; cl = 15 pf. 17. sdo will be high impedance when cs is high. in some systems it may require a pul l-down resister. parameter symbol min typ max unit calibration register write timing data setup time before sclk rising t 29 10 - - ns data hold time after sclk rising t 30 10 - - ns sclk rising to cs rising t 31 10 - - ns sclk(i) sdi cs lsb msb lsb msb command time 8 sclks data time 24 sclks t 30 t 29 t 31 figure 5. sec mode - write timing (not to scale)
CS5560 12 ds713a5 7/31/07 digital characteristics t a = tmin to tmax; vl = 3.3v, 5% or vl = 2.5v, 5% or 1.8v, 5%; vlr = 0v 18. va- and vd- can be any value from 0 to +5v for memory retention. neither va- nor vd- should be allowed to go positive. ain1, ain2, or vref must not be greater than va+ or vd+. this parameter is guaran teed by characterization. digital filter characteristics t a = tmin to tmax; vl = 3.3v, 5% or vl = 2.5v, 5% or 1.8v, 5%; vlr = 0v parameter symbol min typ max unit calibration memory retention (note 18) power supply voltage [v1+ = v2+] ? [v1- = v2-] v mr 4.0 - - v input leakage current i in --2a digital input pin capacitance c in -3-pf digital output pin capacitance c out -3-pf parameter symbol min typ max unit group delay - - 160 - mclks
CS5560 ds713a5 13 7/31/07 guaranteed logic levels t a = -40 to +85 c; v1+ = v2+ = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v; logic 1 = vd+; cl = 15 pf. guaranteed limits parameter sym vl min typ max unit conditions logic inputs minimum high-level input voltage: v ih 3.3 1.9 v 2.5 1.6 1.8 1.2 maximum low-level input voltage: v il 3.3 1.1 v 2.5 0.95 1.8 0.6 logic outputs minimum high-level output voltage: v oh 3.3 2.9 v i oh =-2ma 2.5 2.1 1.8 1.65 maximum low-level output voltage: v ol 3.3 0.36 v i oh =-2ma 2.5 0.36 1.8 0.44
CS5560 14 ds713a5 7/31/07 recommended operating conditions (vlr = 0v, see note 19 ) 19. the logic supply can be any value vl ? vlr = +1.6 to +3.6 volts as long as vlr v2- and vl 3.6 v. 20. the differential voltage reference magnitude is constrained by the v1+ or v1- supply magnitude. absolute maximum ratings (vlr = 0v ) notes: 21. v1+ = v2+; v1- = v2- 22. v1- = v2- 23. transient currents of up to 1 00 ma will not cause scr latch-up. warning: operation beyond these limits may result in permanent damage to the device. parameter symbol min typ max unit single analog supply dc power supplies: (note 19) v1+ v2+ v1- v2- v1+ v2- v1+ v2- 4.75 4.75 - - 5.0 5.0 0 0 5.25 5.25 - - v v v v dual analog supplies dc power supplies: (note 19) v1+ v2+ v1- v2- v1+ v2- v1+ v2- +2.375 +2.375 -2.375 -2.375 +2.5 +2.5 -2.5 -2.5 +2.625 +2.625 -2.625 -2.625 v v v v analog reference voltage (note 20) [vref+] ? [vref-] vref 2.4 4.096 4.2 v parameter symbol min typ max unit dc power supplies: [v1+] ? [v1-] (note 21) vl + [ |v1-| ] (note 22) - - 0 0 - - 5.5 6.3 v v input current, any pin ex cept supplies (note 23) i in --10ma analog input voltage (ain and vref pins) v ina (v1-) ? 0.3 - (v1+) + 0.3 v digital input voltage v ind vlr ? 0.3 - vl + 0.3 v storage temperature t stg -65 - 150 c
CS5560 ds713a5 15 7/31/07 2. overview the CS5560 is a 24-bit analog-to-digital converter cap able of 50 ksps conversion rate. the device is ca- pable of switching multiple input channels at a high rate with no loss in throughput. the adc uses a low-latency digital filter architecture. the filter is des igned for fast settling and settles to full accuracy in one conversion. the converter is a serial output device. the serial po rt can be configured to function as either a master or a slave. the CS5560 provides self-calibration circuitr y to achieve low offset and gain errors. the converter can operate from an analog supply of 5v or from 2.5v. the digital interface supports stan- dard logic operating from 1.8, 2.5, or 3.3 v. the CS5560 converts at 50 ksps when operating from a 16 mhz input clock. 3. theory of operation the CS5560 converter provides high-performance meas urement of dc or ac signals. the converter in- cludes on-chip calibration circuitry to minimize offs et and gain errors. the converter can be used to per- form single conversions or continuous conversi ons upon command. each conversion is independent of previous conversions and can settle to full specified accuracy, even with a full-scale input voltage step. this is due to the converter architecture which us es a combination of a high-speed delta-sigma modulator and a low-latency filter architecture. once power is established to the converter, a reset must be performed. a reset initializes the internal con- verter logic and sets the offset register to zero and the gain register to a decimal value of 1.0. if the cal pin is low when rst transitions from low to high, no calibrati on will be performed. if cal is high when rst goes high, the converter?s offset & gain slope will be calibrated. if conv is held low then the converter will convert continuously with rdy falling every 320 mclks. this is equivalent to 50 ksps if mclk = 16.0 mhz. if conv is tied to rdy , a conversion will occur every 322 mclks. if conv is operated asynchronously to mclk, it may take up to 324 mclks from conv falling to rdy falling. multiple converters can operate synchronously if they are driven by the same mclk source and conv to each converter falls on the same mclk falling edge. alternately, conv can be held low and all devices are reset with rst rising on the same falling edge of mclk. the output coding of the conversion word is a function of the bp/up pin. the active-low sleep signal causes the device to enter a low-power state. the calibration register con- tents are preserved during sleep. when exiting sleep, the converter will take 3083 mclk cycles before conversions can be performed. rst should remain inactive (high) when sleep is asserted (low). 3.1 reset and calibration after the power supplies and the voltage reference are stable, the converter must be reset. the reset func- tion initializes the internal logic in the converter, but does not initiate calibration. after reset has been per- formed, the converter can be used uncalibrated, or calibration can be performed. calibration minimizes offset and gain errors inside the converter. if the dev ice is used without calibration, conversions will in- clude the offset and gain errors of the uncalibrated converter, but the converter will maintain its differential and integral linearity. calibration of of fset and gain can be performed upon command.
CS5560 16 ds713a5 7/31/07 calibration can be initiated in either of two ways. if cal is high when rst transitions from low to high, a calibration cycle will be performed. when calibration is performed, the offset and full-scale points of the converter are calibrated. a calibration cycle takes 327,680 mclk cycles. the rdy signal falls upon com- pletion of reset and calibration se quence. if cal is held low when rst transitions from low to high, no calibration will be performed. calibrations can be initia ted any time the converter is idle by taking the cal input high. rdy will fall at the end of the calibration cycl e. the cal pin should be returned low when not being used. a calibration cycle calibrates the offset and full-scal e points of the converter transfer function. when the offset portion of the calibration is performed, the ai n+ and ain- pins are disconnected from the input and shorted internally. the offset of the converter is th en measured and a correction factor is stored in the offset calibration register. then the voltage reference is internally connected to act as the input signal to the converter and a gain calibration is performed. the gain correction results are placed in the gain cali- bration register. the contents of the 24-bit offset and gain registers are used to map the conversion data prior to its output from the converter. the offset and gain calibration registers can be read and written if desired. to read or write the calibration registers inside of the converter, the converter must be idle, and the serial port must be in the sec mode (smode = vlr). table 1 depicts the commands necessary to read or write the calibration registers. 3.1.1 offset register the offset register maps one for one with the conversi on word when the gain register is set to 1 decimal. after reset all bits are zero. 3.1.2 gain register the gain register spans from 0 to (8 - 2 -21 ). after reset, bit d22 is 1, all others are 0. this results in a dec- imal gain value of 1.000....000. table 1. offset & gain calibration register read/write commands register read command write command offset register 0x40 0xc0 gain register 0x20 0xa0 msb d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 sign 2 -2 2 -12 000000000000 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb 2 -11 2 -24 000000000000 msb d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 001000000000 d12d11d10d9d8d7d6d5d4d3d2lsb 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 000000000000
CS5560 ds713a5 17 7/31/07 the on-chip calibration registers can be read or written via the serial port. reading or writing into the cal- ibration registers requires that the serial port be in the sec mode. to write into the offset or gain register, the appropriate 8-bit command (see table 1 on page 16) is first shifted into the sdi pin. rising edges of sclk latch the bits. to perform a write, the 8-bit co mmand is immediately followed by the 24 bit data word to be written. when a read command is used, the 24 bit data word from the register will be output from the sdo pin. the data bits will be output on rising e dges of sclk. the data bits have sufficient hold time to be latched externally by the next rising edge of sclk. 3.2 conversion the CS5560 converts at 50 ksps when synchronously operated (conv = vlr) from a 16.0 mhz master clock. conversion is initiated by taking conv low. a conversion lasts 320 master clock cycles, but if conv is asynchronous to mclk there may be an unc ertainty of 0-4 mclk cycles after conv falls to when a conversion actually begins. this may extend the throughput to 324 mclks when the conversion is completed, the output word is placed into the serial port and rdy goes low. to convert continuously, conv should be held low. in conti nuous conversion mode with conv held low, a conversion is performed in 320 mclk cycles. alternately rdy can be tied to conv and a conversion will occur every 322 mclk cycles. to perform only one conversion, conv should return high at least 20 master clock cycles before rdy falls. once a conversion is completed and rdy falls, rdy will return high when all the bits of the data word are emptied from the serial port or if the conversion data is not read and cs is held low, rdy will go high two mclk cycles before the end of conversion. rdy will fall at the end of the next conversion when new data is put into the port register. see serial port on page 24 for information about reading conversion data. conversion performance can be affected by several fact ors. these include the choice of clock source for the chip, the timing of conv , and the choice of the serial port mode. the converter can be operated from an internal oscill ator. this clock source has greater jitter than an external crystal-based clock. jitter may not be an issue when measuring dc signals, or very-low-fre- quency ac signals, but can become an issue for higher frequency ac signals. for maximum performance when digitizing ac signals, a low-jitter mclk should be used. to maximize performance, the conv pin should be held low in the co ntinuous conversion state to per- form multiple conversions, or conv should occur synchronous to mclk , falling when mclk falls. if the converter is operated at maximum throughput, the ssc serial port mode is less likely to cause in- terference to measurements as the sclk output is synchronized to the mclk. alternately, any interfer- ence due to serial port clocking can also be minimize d if data is read in the sec serial port mode when a conversion is not is progress. 3.3 clock the CS5560 can be operated from its internal oscillator or from an external master clock. the state of mclk determines which clock source will be used. if mclk is tied low, the internal oscillator will start and be used as the clock source for the converter. if an external cmos-compatible clock is input into mclk the converter will power down the internal oscillator and use the external clock. if the mclk pin is held high, the internal oscillator will be held in the stopped state. the mclk input can be held high to delete clock cycles to aid in operating multiple converters in different phase relationships.
CS5560 18 ds713a5 7/31/07 the internal oscillator can be used if the signals to be measured are essentially dc. the internal oscillator exhibits jitter at about 500 picoseconds rms. if the cs 5560 is used to digitize ac signals, an external low-jitter clock source should be used. if the internal oscillator is used as the clock for t he CS5560, the maximum conversion rate will be dictated by the oscillator frequency. 3.4 voltage reference the voltage reference for the CS5560 can range from 2.4 volts to 4.2 volts. a 4.096 volt reference is re- quired to achieve the specified performance. figure 7 and figure 8 illustrate the connection of the voltage reference with either a single +5 v analog supply or with 2.5 v. for optimum performance, the voltage reference device should be one that provides a capacitor connec- tion to provide a means of noise filt ering, or the output should include so me type of bandwidth-limiting fil- ter. some 4.096 volt reference devices need only 5 volts total supply for operation and can be connected as shown in figure 7 or figure 8 . the reference should have a local bypass capacitor and an appropriate output capacitor. some older 4.096 voltage reference designs require more headroom and must operate from an input volt- age of 5.5 to 6.5 volts. if this type of voltage reference is used ensure that when power is applied to the system, the voltage reference rise time is slower than the rise time of the v1+ and v1- power supply volt- age to the converter. an example circuit to slow the output startup time of the reference is illustrated in figure 6 . figure 6. voltage reference circuit 3.5 analog input the analog input of the converter is fully differential with a peak input of 4.096 volts on each input. this is illustrated in figure 7 and figure 8 . these diagrams also illustrate a differential buffer amplifier configura- tion for driving the CS5560. the capacitors at the outputs of the amplifiers provide a charge reservoir for the dynamic current from the a/d inputs while the resistors isolate the dynamic curr ent from the amplifier. the amplifiers can be pow- ered from higher supplies than those used by the a/d but precautions should be taken to ensure that the op amp output voltage remains within the power supply limits of the a/d, especially under start-up condi- tions. 2k 10 f 5.5 to 15 v vin vout gnd 4.096 v refer to v1- and vref1 pins.
CS5560 ds713a5 19 7/31/07 3.6 output coding format the reference voltage directly defines the input voltage range in both the unipolar and bipolar configura- tions. in the unipolar configuration (bp/up low), the first code transition oc curs 0.5 lsb above zero, and the final code transition occurs 1.5 lsbs below vref. in the bipolar configuration (bp/up high), the first code transition occurs 0.5 lsb above -vref and the last transition occurs 1.5 lsbs below +vref. see table 2 for the output coding of the converter. note: vref = (vref+) - (vref-) table 2. output coding, two?s complement bipolar input voltage two?s complement >(vref-1.5 lsb) 7f ff ff vref-1.5 lsb 7f ff ff 7f ff fe -0.5 lsb 00 00 00 ff ff ff -vref+0.5 lsb 80 00 01 80 00 00 <(-vref+0.5 lsb) 80 00 00 note: vref = (vref+) - (vref-) table 3. output c oding, offset binary unipolar input voltage offset binary >(vref-1.5 lsb) ff ff ff vref-1.5 lsb ff ff ff ff ff fe (vref/2)-0.5 lsb 80 00 00 7f ff ff +0.5 lsb 00 00 01 00 00 00 <(+0.5 lsb) 00 00 00
CS5560 20 ds713a5 7/31/07 3.7 typical connection diagrams the following figure depicts the CS5560 powered from bipolar analog supplies, +2.5 v and - 2.5 v. figure 7. CS5560 configured using 2.5v analog supplies vref- vref+ +4.096 voltage reference (note 1) +2.5 v smode cs 4 sclk 4 sdo rdy conv cal mclk sleep rst bp/up 1. see section 3.4 voltage reference for information on required voltage reference performance criteria. 2.locate capacitors so as to minimize loop length. 3. the 2.5 v supplies should also be bypassed to ground at the converter. 4. vlr and the power supply ground for the 2.5 v should be connected to the same ground plane under the chip. 5. sclk and sdo may require pull-down resistors in some applications. 6. an rc input filter can be used to band limit the input to reduce noise. select r to be equal to the parallel combination of the feedback of the feedback resistors 4.99k || 4.99k = 2.5k ?? notes -2.5 v bufen (v-) buffers off (v+) buffers on 10 f0.1 f v1+ v2+ v1- v2- vl vlr dcr +2.5 v +3.3 v to +1.8 v 0.1 f 0.1 f x7r 0.1 f 10 -2.5 v CS5560 tst 10 0.1 f ain- ain+ 49.9 60pf 4.99k 4700pf c0g 49.9 60pf 4.99k 4700pf c0g 4.99k 4.99k -2.048 v +2.048 v 0 v +2.048 v -2.048 v 0 v r 1 r 1 c 1 c 1
CS5560 ds713a5 21 7/31/07 the following figure depicts the CS5560 devic e powered from a single 5v analog supply. figure 8. CS5560 configured using a single 5v analog supply ain- ain+ smode cs 3 sclk 3 sdo rdy conv cal bp/up mclk sleep rst tst vref- vref+ +4.096 voltage reference (note 1) +5 v bufen 1. see section 3.4 voltage reference for information on required voltage reference performance criteria. 2. locate capacitors so as to minimize loop length. 3. v1-, v2-, and vlr should be connected to the same ground plane under the chip. 4. sclk and sdo may require pull-down resistors in some applications. notes 0.1 f (v-) buffers off (v+) buffers on 0.1 f 10 f v1+ v2+ v1- v2- vl vlr dcr +5 v +3.3 v to 1.8 v 0.1 f 0.1 f x7r 0.1 f 10 CS5560 49.9 47pf 4.99k 4700pf c0g 49.9 47pf 4.99k 4700pf c0g -0.452 v 4.548 v 2.5 v +4.548 v -0.452 v 2.5 v 2.048 v 4.096 v
CS5560 22 ds713a5 7/31/07 3.8 ain & vref sampling structures the CS5560 uses on-chip buffers on the ain+, ain-, and the vref+ inputs. buffers provide much higher input impedance and therefore reduce the amount of driv e current required from an external source. this helps minimize errors. the buffer enable (bufen) pin determines if the on-ch ip buffers are used or not. if the bufen pin is connected to the v1+ supply the buffe rs will be enabled. if the bufen pin is connected to the v1- pin the buffers are off. the converter will consume about 30 mw less power when the buffers are off, but the input impedances of ain+, ain- and vref+ will be significantly less than with the buffers enabled. 3.9 converter performance the CS5560 achieves excellent differential nonlinearity ( dnl) as shown in figure 9. figure 9 illustrates the code widths on the typical scale of 1 lsb and on a zoomed scale of 0.2 lsb. figure 9. CS5560 dnl plot (zoom view)
CS5560 ds713a5 23 7/31/07 3.10 digital filt er characteristics the digital filter is designed for fast settling, therefor e it exhibits very little in-band attenuation. the filter attenuation is 1.040 db at 25 khz when sampling at 50 ksps. figure 10. CS5560 spectral response (dc to fs/2) figure 11. CS5560 spectral response (dc to 5 khz) figure 12. CS5560 spectral response (dc to 4fs) -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0 5k 10k 15k 20k 25k frequency (hz) attenuation (db) -0.0414 db -0.166 db -0.3725 db -0.664 db -1.040 db fs = 50 ksps frequency (hz) -0.001646 db -0.00663 db -0.0149 db -0.0262 db -0.0414 db fs = 50 ksps fs = 50 ksps
CS5560 24 ds713a5 7/31/07 3.11 serial port the serial port on the CS5560 can operate in two different modes: synchronous self clock (ssc) mode & synchronous external clock (sec) mode. the serial por t must be placed into the sec mode if the offset and gain registers of the converter are to be read or written. the converter must be idle when reading or writing to the on-chip registers. 3.11.1 ssc mode if the smode pin is high (smode = vl), the serial port operates in the ssc (synchronous self clock) mode. in the ssc mode the port shi fts out conversion data words with sclk as an output. sclk is gen- erated inside the converter from mclk. data is output from the sdo (serial data output) pin. if cs is high, the sdo and sclk pins will stay in a high-impedance state. if cs is low when rdy falls, the con- version data word will be output from sdo msb first. da ta is output on the rising edge of sclk and should be latched into the external logic on the subsequent rising edge of sclk. when all bits of the conversion word are output from the port the rdy signal will return to high. 3.11.2 sec mode if the smode pin is low (smode = vlr), the serial port operates in the sec (synchronous external clock mode). in this mode, the user usually monitors rdy . when rdy falls at the end of a conversion, the conversion data word is placed into the output data register in the serial port. cs is then activated low to enable data output. note that cs can be held low continuously if it is not necessary to have the sdo output operate in the high impedance state. when cs is taken low (after rdy falls) the conversion data word is then shifted out of the sdo pin by driving the sclk pin from system logic external to the converter. the sdi input must be held low when reading conversion word data. data bits are advanced on rising edges of sclk and latched by the subsequent rising edge of sclk. if cs is held low continuously, the rdy signal will fall at the end of a conversion and the conversion data will be placed into the serial port. if the user starts a read, the user will maintain control over the serial port until the port is empty. however, if sclk is not toggled, the converter will overwrite the conversion data at the completion of the next conversion. if cs is held low and no read is performed, rdy will rise just prior to the end of the next conversion and then fall to signal that new data has been written into the serial port.
CS5560 ds713a5 25 7/31/07 3.12 power supplies & grounding the CS5560 can be configured to operate with its anal og supply operating from 5v, or with its analog sup- plies operating from 2.5v. the digital interface supports digital logic operating from either 1.8v, 2.5v, or 3.3v. figure 7 on page 20 illustrates the device configured to operate from 2.5v analog. figure 8 on page 21 illustrates the device configured to operate from 5v analog. to maximize converter performance, the analog groun d and the logic ground for the converter should be connected at the converter. in the dual analog supply configuration, the analog ground for the 2.5v sup- plies should be connected to the vlr pin at the conver ter with the converter placed entirely over the an- alog ground plane. in the single analog supply configuration (+5v), the ground for the +5v supply should be directly tied to the vlr pin of the converter with the converter pl aced entirely over the analog ground plane. refer to figure 8 on page 21.
CS5560 26 ds713a5 7/31/07 3.13 using the CS5560 in mu ltiplexing applications the CS5560 is a delta-sigma a/d converter. delta- sigma converters use oversampling as means to achieve high signal to noise. this means that once a conversion is started the converter takes many sam- ples to compute the resulting output word. the analog input for the signal to be converted must remain active during the entire conversion until rdy falls. the CS5560 can be used in multiplexing applications , but the system timing for changing the multiplexer channel and for starting a new conversion will depend upon the multiplexer system architecture. the simplest system is illustrated in figure 13 . any time the multiplexer is changed, the analog signal presented to the converter must fully settle. after the signal has settled, the conv signal is issued to the converter to start a conversion. being a delta-sigma c onverter, the signal must remain present at the input of the converter until the conversion is completed. once the conversion is completed, rdy falls. at this time the multiplexer can be changed to the next channel and the data can be read from the serial port. the conv signal should be delayed until after the data is read and until the new analog signal has settled. in this configuration, the throughput of the converter will be dictated by the settling time of the analog input circuit and the conversion time of the converter. the conversion data can be read from the serial port after the multiplexer is changed to the new channel while the analog input signal is settling. figure 13. simple multiplexing scheme a more complex multiplexing scheme can be used to incr ease the throughput of the converter is illustrated in figure 14 . in this circuit, two banks of multiplexers are used. cs556x ain+ ain- 49.9 60pf 4.99k 4700pf c0g 49.9 60pf 4.99k 4700pf c0g ch1+ ch2+ ch3+ ch4+ ch1- ch2- ch3- ch4- amplifier settling time conversion time amplifier settling time ch1 ch2 conv rdy advance mux throughput
CS5560 ds713a5 27 7/31/07 at the same time the converter is performing a conv ersion on a channel from one bank of multiplexers, the second multiplexer bank is used to select the ch annel for the next conversion. this configuration al- lows the buffer amplifier for the second multiplexer bank to fully settle while a conversion is being per- formed on the channel from the first multiplexer bank. the multiplexer on the output of the buffer amplifier and the conv signal can be changed at the same time in this configuration. this multiplexing architec- ture allows for maximum multiplexing throughput from the a/d converter.the following figure depicts the recommended analog input amplifier circuit. figure 14. more complex multiplexing scheme 3.14 synchronizing multiple converters many measurement systems have multiple converte rs that need to operate synchronously. the convert- ers should all be driven from the same master clock. in this configuration, the converters will convert syn- chronously if the same conv signal is used to drive all the converters, and conv falls on a falling edge of mclk. if conv is held low continuously, reset (rst ) can be used to synchronize multiple converters if rst is released on a falling edge of mclk. cs556x ain+ ain- 49.9 60pf 4.99k 4700pf c0g 49.9 60pf 4.99k 4700pf c0g 49.9 60pf 4.99k 4700pf c0g 49.9 60pf 4.99k 4700pf c0g b1+ b2+ b1- b2- ch1 ch2 c1+ c2+ c1- c2- ch3 ch4 sw2 sw3 sw1 a1+ a2+ a1- a2- conv convert on ch1 convert on ch1 convert on ch4 convert on ch2 convert on ch3 select a1 select a2 select a1 select a2 select b1 select b2 select b1 select a1 select c1 select c2 select c1 sw1 sw2 sw3
CS5560 28 ds713a5 7/31/07 4. pin descriptions cs ? chip select, pin 1 the chip select pin allows an external device to access the serial port. if smode = vl (ssc mode) and cs is held high, the sdo output and the sclk output will be held in a high-impedance output state. sdi ? serial data input, pin 2 sdi is the input pin for reading and writing calibration registers vi a the serial port. sdi is only accessible when smode is set to enable the sec se rial mode. data is shif ted into this pin by sclk. sdi should be held low when the serial port is in ssc mode. smode ? serial mode select, pin 3 the serial interface mode pin (smode) dictates wh ether the serial port behaves as a master or slave interface.if smode is ti ed high (to vl), the port w ill operate in th e synchronous self-clocking (ssc) mode. in ssc mode the port acts as a master in which the converter out- puts both the sdo and sclk signals. if smode is ti ed low (to vlr) the port will operate in the synchronous external clocking (sec) mode. in se c mode, the port acts as a slave in which the external logic or microcontroller generates the sclk used to output the conversion data word from the sdo pin. ain+, ain- ? differential analog input, pin 4, 5 ain+ and ain- are differential inputs for the converter. v1- ? negative power 1, pin 6 the v1- and v2- pins provide a negative supply voltage to the core circuitry of the chip. these two pins should be decoupled as shown in the application block diagrams. v1- and v2- should be supplied from the same source voltage. for single supply operation these two voltages are nominally 0 v (ground). for dual supply operation they are nominally -2.5 v. v1+ ? positive power 1, pin 7 the v1+ and v2+ pins provide a positive supply vo ltage to the core circui try of the chip. these two pins should be decoupled as shown in the application block diagrams. v1+ and v2+ should be supplied from the same source voltage. for single supply operation these two voltages are nominally +5 v. for dual supply operation they are nominally +2.5 v. bufen ? buffer enable, pin 8 buffers on input pins ain+ and ain- are enabled if bufen is connected to v1+ and disabled if connected to v1-. sleep 12 sleep mode select bp/up 11 bipolar/unipolar select vref- 10 voltage reference input vref+ 9 voltage reference input bufen 8 buffer enable v1+ 7 positive power 1 v1- 6 negative power 1 ain- 5 differential analog input ain+ 4 differential analog input 3 2 cs 1 chip select rst 13 reset cal 14 calibrate conv 15 convert dcr 16 digital core regulator v2+ 17 positive voltage 2 v2- 18 negative voltage 2 mclk 19 master clock vlr 20 logic interface return vl 21 logic interface power sdo 22 serial data output sclk 23 serial clock input/output rdy 24 ready sdi serial data input smode serial mode select
CS5560 ds713a5 29 7/31/07 vref+, vref- ? voltage reference input, pin 9, 10 a differential voltage reference input on these pins functions as the vo ltage reference for the converter. the voltage between these pins can range between 2.4 volts and 4.2 volts, with 4.096 volts being the nominal reference voltage value. bp/up ? bipolar/unipola r select, pin 11 the bp/up pin determines the span and the output coding of the converter. when set high to select bp (bipolar), the input span of the converter is -4.096 volts to +4.096 volts fully differential (assuming the voltage reference is 4.096 volts) and outputs data is coded in two's complement format. when set low to select up (unipolar), the input span is 0 to +4.096 fully differential and the output data is coded in binary format. sleep ? sleep mode select, pin 12 when taken low, the sleep pin will cause the conv erter to enter into a low-power state. sleep will stop the internal osc illator and powe r down all internal analog circuitry. rst ? reset, pin 13 reset is necessary after powe r is initially applied to th e converter. when the rst input is taken low, the logic in the converter will be reset. when rst is released to go high, certain portions of the analog circuitry are started. rdy falls when rese t is complete. cal ? calibrate, pin 14 after power is applied, a reset should be performe d prior to calibration. af ter an initial reset, cal- ibration can be performed at any time. calibration can be initiated in either of two ways. if cal is high when coming out of reset, (rst going high), a calibration will be performed. if rst is taken high with cal low, a calibration is not performed, but calibration can be initiated by taking cal high at any time the converter is idle. rdy will also fall when calib ration is completed. conv ? convert, pin 15 the conv pin initiates a conversion cycle if taken lo w, unless a calibration cycle or a previous conversion is in progress. when the conversion cycle is completed, the conversion word is out- put to the serial port register and the rdy signal goes low. if conv is held low and remains low when rdy falls another conversion cycle will be started. dcr ? digital core regulator, pin 16 dcr is the output of the on-chip regulator for the digital logic core. dcr should be bypassed with a capacitor to v2-. the dcr pin is not designed to power any external load. v2+ ? positive power 2, pin 17 the v1+ and v2+ pins provide a positive supply voltage to the circuitry of the chip. these two pins should be decoupled as shown in the application block diagrams. v1+ and v2+ should be supplied from the same source voltage. for single supply operation these two voltages are nominally +5 v. for dual supply operation they are nominally +2.5 v. v2- ? negative power 2, pin 18 the v1- and v2- pins provide a negative supply voltage to the circuitry of the chip. these two pins should be decoupled as shown in the app lication block diagrams. v1- and v2- should be supplied from the same source voltage. for single supply operation these two voltages are nominally 0 v (ground). for dual supply operation they are nominally -2.5 v. mclk ? master clock, pin 19 the master clock pin (mclk) is a multi-function pin. if tied low (mclk = vlr) the on-chip oscil- lator will be enabled. if tied high (mclk = vl), all clocks to the in ternal circuitry of the converter will stop. when mclk is held high the internal oscillator will also be stopped. mclk can also function as the input for an external cmos-compa tible clock that conforms to supply voltages on the vl and vlr pins.
CS5560 30 ds713a5 7/31/07 vlr, vl ? logic interface power/return, pin 20, 21 vl and vlr are the supply voltages for the digital logic interface. vl and vlr can be config- ured with a wide range of common mode voltage. the following interface pins function from the vl/vlr supply: smode, cs , sclk, sdi, sdo, rdy , sleep , conv , rst , conv, cal, bp/up , and mclk. sdo ? serial data output, pin 22 sdo is the output pin for the serial output port. data from this pi n will be output at a rate deter- mined by sclk and in a format determined by the bp/up pin. data is output msb first and advances to the next data bit on the rising edge s of sclk. sdo will be in a high impedance state when cs is high. sclk ? serial clock input/output, pin 23 the smode pin determines whether the sclk signal is an input or an output signal. sclk determines the rate at which data is clocked ou t of the sdo pin. if the converter is in ssc mode, the sclk frequency will be determined by the master clo ck frequency of the converter (either mclk or the internal os cillator). in sec mode , the user determines the sclk frequency. if smode = vl (ssc mode), sclk will be in a high-imped ance state when cs is high. rdy ? ready, pin 24 the rdy signal rises when a calibration is initiated. when the calibration is ne ar completion the state of conv is examined. if conv is high, the rdy signal will fall upon the completion of cal- ibration. if conv is low the converter will immediately start a conversion and rdy will remain high until the conversion is completed. at the end of any conversion rdy falls to indicate that a conversion word has been placed into the serial port. rdy will return high after all data bits are shifted out of the serial port or two master clock cycles before new data becomes available if the cs pin is inactive (high); or tw o master clock cycles before new data becomes available if the user holds cs low but has not started reading the data from the converter when in sec mode.
CS5560 ds713a5 31 7/31/07 5. package dimensions notes: 1.?d? and ?e1? are reference datums and do not included mold flas h or protrusions, but do include mold mismatch and are measure d at the parting line, mold flash or prot rusions shall not exceed 0.20 mm per side. 2.dimension ?b? does not include dambar protrusion/intrusion. al lowable dambar protrusion shall be 0.13 mm total in excess of ?b ? dimension at maximum material condition. dambar intrusion shall not reduce di mension ?b? by more than 0.07 mm at least material condition. 3.these dimensions apply to the flat section of the lead betw een 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.13 0.25 a2 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.311 0.323 0.335 7.90 8.20 8.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.03 0.041 0.63 0.75 1.03 0 4 8 0 4 8 jedec #: mo-150 controlling dimensio n is millimeters. 24l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
CS5560 32 ds713a5 7/31/07 6. ordering information 7. environmental, manufact uring, & handlin g information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. 8. revision history model linearity temperature conversion time throughput package CS5560-isz 0.0007% -40 to +85 c 20 s 50 ksps 24-pin ssop model number peak reflow temp msl rating* max floor life CS5560-isz 260 c 3 7 days revision date changes a1 may 2007 advance release. a2 jun 2007 updated serial interface timing parameters. a3 jun 2007 added dnl plot. a4 jun 2007 updated typical connection diagram. a5 aug 2007 corrected liearity spec. in ordering information section. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information be ing relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this informatio n as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve po tential risks of deat h, personal injury, or severe prop- erty or environmental damage ("critical applications"). cirrus products are not de signed, authorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, automotive safety or security de- vices, life support products or other critical applications. i nclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and ma kes no warranty, express, statut ory or implied, including the implied warranties of merchantability and fi tness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or custom er's customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, includi ng attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trade marks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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